1. Field of the Invention
This invention relates to a test pattern generating apparatus, a circuit designing apparatus, a test pattern generating method, a circuit designing method, a test pattern generating program and a circuit designing program for generating test patterns to be used for judging if a manufactured LSI is acceptable or unacceptable from the circuit data of the designed LSI.
2. Description of Related Art
Firstly, a known test pattern generating apparatus will be described by referring to FIG. 7 of the accompanying drawings. FIG. 7 is a schematic block diagram of a known test pattern generating apparatus, showing its configuration. The test pattern generating apparatus 102 comprises a circuit data read in section 11 and a test pattern generating section 13. The circuit data read in section 11 is connected to an external circuit data storage section 1 while the test pattern generating section 13 is connected to an external test pattern storage section 3.
Now, the operation of the known test pattern generating apparatus will be described below. The circuit data of a designed LSI is stored in the circuit data storage section 1. The circuit data read in section 11 reads in the circuit data from the circuit data storage section 1 and prepares an FF (flip flop) list showing flip flops sorted for each functional block. The prepared FF list is output to the test pattern generating section 13. Then, the test pattern generating section 13 generates a test pattern for each functional block according to the FF list and stores the generated test patterns in the test pattern storage section 3.
Known techniques relating to the present invention include one described in Japanese Patent Application Laid-Open Publication No. 11-287847 (pp 3-5, FIG. 1), which discloses a test pattern preparing apparatus. The disclosed test pattern preparing apparatus can reduce the total volume of data necessary for managing test patterns and improve the efficiency of the operation of modifying test patterns as it is adapted to prepare a test pattern by combining block patterns according to configuration information.
However, the known test pattern generating apparatus generates test patterns for all the functional blocks without discriminating the internals of functional blocks. Since the number of functional blocks and that of gates mounted in an LSI are ever increasing, there arises a problem that the processing time and the occupied memory area increase explosively if test patterns are generated for all the functional blocks.